System Architecture — Concept

Kestrel K1

How the SoC, memory, storage, display, input, audio, and power subsystems wire together — plus every discrete peripheral in the build.

Spec Sheet / Architecture

Document KST-ARCH-001
Revision A
Issued 2026-08-31
Status Concept — pre-production

System Architecture

The SoC sits as the single hub — every other subsystem talks to it over one dedicated bus rather than sharing lines. Controls and audio are each aggregated by a small local controller first, so the application processor only ever sees a handful of high-level buses instead of dozens of raw GPIOs.

System block diagram — the Kestrel Silicon KX2 as the single hub, with each subsystem attached over one dedicated bus. The audio codec and input MCU each aggregate several physical peripherals before reporting to the SoC.

Why a separate input MCU: polling two analog sticks, two triggers, and eight buttons directly from the application processor would keep it out of its lowest power states. A small always-on MCU debounces and samples locally, then reports over SPI — and can wake the SoC from sleep on a single button press.

Memory Architecture

CPU, GPU, and ISP share one 8 GB LPDDR5 pool over a common 2-channel bus — there's no separate VRAM to size around. The OS carves out fixed reservations at boot; everything else is available to whichever app or game is in the foreground.

Region	Size	Share	Purpose
OS & Reserved	1.5 GB	18.75%	Kernel, drivers, launcher, always-resident services
GPU Frame Buffer	2.0 GB	25%	Render targets, textures, graphics working set
App / Game Heap	4.0 GB	50%	Available to the foreground title
Quick-Resume Cache	0.5 GB	6.25%	Snapshot of one suspended app for instant resume

Bandwidth: LPDDR5-6400, 2×16-bit channels (32-bit total) — 25.6 GB/s peak, shared by CPU, GPU, ISP, and DMA rather than partitioned per block.

Peripheral List

Every discrete component the block diagram above compresses into eight boxes, with its function, host interface, and quantity.

Compute & Memory

Peripheral	Function	Interface	Qty
Kestrel Silicon KX2	Application SoC — CPU, GPU, ISP, security enclave	Package-level	1
LPDDR5 DRAM	Unified system memory, PoP-stacked on SoC — see §02	LPDDR5, 2ch	8 GB
UFS 3.1 flash	Internal storage	UFS 3.1 (M-PHY)	128/256 GB
microSD slot	Removable storage expansion	SD 4.0	1

Display

Peripheral	Function	Interface	Qty
5.5″ IPS panel	Primary display, 1280×720	MIPI-DSI, 4-lane	1
Display driver IC	Panel timing, gamma, backlight PWM	Embedded in module	1

Input & Haptics

Peripheral	Function	Interface	Qty
Input MCU	Aggregates all controls, reports HID, wakes SoC	SPI (to SoC)	1
Analog stick (TMR)	Dual-axis directional input, drift-resistant	Analog (to MCU)	2
D-pad module	8-way digital directional input	GPIO (to MCU)	1
Face button switch	△ ○ ✕ □ input	GPIO (to MCU)	4
Shoulder button (L1/R1)	Digital shoulder input	GPIO (to MCU)	2
Shoulder trigger (L2/R2)	Analog trigger input	Analog (to MCU)	2
Volume rocker	Volume up/down	GPIO (to MCU)	1
Power / capture button	System power/lock, screenshot capture	GPIO (to MCU)	2
Haptic LRA actuator	Linear resonant vibration feedback	PWM/I2C (to MCU)	2

Audio

Peripheral	Function	Interface	Qty
Audio codec + amp	Stereo DAC/ADC, speaker amplification	I2S (to SoC)	1
Stereo speaker	Front-firing audio output	Analog (to codec)	2
Beamforming mic	Voice capture, noise rejection	PDM (to codec)	2
3.5mm headphone jack	Wired audio out, in-line remote	Analog + I2C detect	1

Connectivity & Power

Peripheral	Function	Interface	Qty
Wi-Fi 6 / BT 5.3 module	Wireless networking and accessory pairing	SDIO 3.0 + UART	1
USB-C controller	Data, charging, DisplayPort Alt Mode	USB 3.1 Gen1 + DP Alt	1
USB-C connector	Physical charge/data/video port	—	1
PMIC	Power sequencing, voltage rails, battery gauge	I2C (to SoC)	1
Battery charge IC	USB-C PD fast-charge management	I2C (to PMIC)	1
LiPo battery cell	Main power source, user-replaceable	Power rail	4,500 mAh

Cost Reference

Engineering-estimate BOM at concept stage, not sourced from live distributor quotes — treat it as a feasibility envelope, not a costing you'd order against.

Component	Category	Est. Unit Cost
Kestrel Silicon KX2 SoC	Compute	$18.00
LPDDR5 8GB (PoP)	Compute	$9.50
UFS 3.1 256GB flash	Compute	$14.00
microSD slot	Compute	$0.35
5.5″ IPS display module	Display	$11.50
Input MCU	Input	$0.60
Analog stick (TMR) ×2	Input	$2.40
D-pad + face buttons	Input	$0.80
Shoulder buttons/triggers	Input	$1.10
Haptic LRA ×2	Input	$1.40
Audio codec + amp	Audio	$1.80
Speakers ×2	Audio	$1.80
Mic array ×2	Audio	$0.80
Headphone jack	Audio	$0.25
Wi-Fi/BT combo module	Connectivity	$4.50
USB-C controller + connector	Connectivity	$1.60
PMIC	Power	$2.20
Battery charge IC	Power	$0.90
LiPo battery cell (4,500mAh)	Power	$6.80
Enclosure (shell + mid-frame)	Mechanical	$7.50
PCB, passives & assembly	Mechanical	$9.00

Total est. BOM: ~$96.80 per unit at low volume. Excludes packaging and fulfillment. The SoC, display module, and battery cell carry the most pricing risk — none of these are bulk-catalog parts, so real quotes at target volume would likely move the total meaningfully in either direction.

Kestrel K1 — System Architecture Rev A Figures are pre-production targets, subject to change