Whether an updatable soft CPU core / eFPGA fits Kestrel's power envelope — and why the same fabric is a better fit for an AI or robotics platform than for a gaming handheld.
Kestrel Silicon KX2 (the concept ARM part in the architecture doc) doesn't exist yet — same problem the SteamOS POC works around for launcher/UX validation. An "updatable soft CPU core on FPGA" looked like a possible way to sidestep committing to fixed silicon for compute too: build the main processor as reconfigurable fabric, patch it post-ship instead of taping out again. This doc checks whether that actually works for Kestrel, and where it does work.
A soft core runs on generic LUTs and reconfigurable routing instead of custom-laid-out transistors — that generality is what makes it reconfigurable, and it costs on two axes from the same root cause: more transistors switch per logic operation than a hardened gate doing the same job (power), and the same routing adds propagation delay to the critical path (max clock frequency). The two aren't independent problems — pushing clock speed to compensate for weak throughput just makes the power problem worse.
| Part | Reconfigurable ("soft") mode | Hardened mode on the same die |
|---|---|---|
| Efinix Sapphire RISC-V SoC | 20–400 MHz, patchable | Up to 1 GHz quad-core, fixed at fab time |
| Company | Product | Category | Notes |
|---|---|---|---|
| AMD (Xilinx) | MicroBlaze V | Soft-core IP | RISC-V soft core for adaptive SoCs/FPGAs |
| Intel (Altera) | Nios V | Soft-core IP | ~5× perf of Nios II/e, still soft-core class |
| Microchip | Mi-V ecosystem | Soft-core IP + hard RISC-V | PolarFire SoC pairs hard RISC-V cores with fabric |
| Efinix | Sapphire RISC-V SoC | Soft + hard core | See §02 — same family, two very different tradeoffs |
| Lattice | SiFive E2 (partner IP) | Soft-core IP | Targets Lattice FPGAs via SiFive collaboration |
| Achronix | Speedcore eFPGA | eFPGA-in-ASIC | Licensable fabric embedded directly in a custom ASIC |
| Flex Logix | EFLX1K / EFLX4K | eFPGA-in-ASIC | Tileable eFPGA cores for ASIC/SoC integration |
| QuickLogic | EOS S3 | MCU + small eFPGA | Cortex-M4F + eFPGA glue logic, always-on voice/sensor class |
| AMD (Xilinx) | Kria K26 SOM | Hard CPU + fabric | Zynq UltraScale+: hard Cortex-A53/R5 + FPGA, ROS 2 support |
Checked against the SoC power budget in the architecture doc's §03 (1,150 mW mixed gaming / 2,050 mW peak / 480 mW video) and the ~45 mW whole-system suspend baseline.
| Candidate | Fits the power budget? | Why it still doesn't work as the main CPU |
|---|---|---|
| Efinix Titanium/Sapphire (soft mode) | Unverified — no published Icc table | Even if power fits, 20–400 MHz is too slow to drive a modern gaming UI/OS smoothly |
| QuickLogic EOS S3 | Trivially, <300µW | Wrong product class entirely — an MCU+sensor-fusion part, not an application processor |
The fix isn't a better chip generation — it's that AI/robotics workloads don't route through a soft CPU's scalar instruction pipeline at all. The natural implementation is dataflow: dedicated parallel pipelines built directly in the fabric, next to a hardened CPU doing orchestration.
| Workload | Why the fabric helps |
|---|---|
| NN inference / sensor fusion math | Dense MAC is what DSP blocks are built for — e.g. Efinix Ti60 has 160 DSP blocks, each capable of INT8 quad-multiply or a fused BFLOAT16 multiply-add in hardware |
| Motor/sensor control loops | Cycle-accurate, deterministic timing — no OS/RTOS scheduler jitter, a real capability advantage independent of power |
| Sensor bridging | Many simultaneous parallel I/O interfaces without contending for a shared bus/DMA like an MCU would |
| Part | Role in an AI/robotics platform |
|---|---|
| AMD Kria K26 SOM | Hard Cortex-A53/R5 + fabric, ROS 2-ready — the reference heterogeneous pattern |
| Microchip PolarFire SoC | Hard RISC-V + fabric, real-time control + reconfigurable I/O as the core pitch |
| Efinix Sapphire | Same chip as §02, but here the BFLOAT16 DSP path is the point, not soft-core clock speed |
| Lattice CrossLink-NX / CertusPro-NX | Low-power edge AI/vision sensor bridging |
| QuickLogic EOS S3 | Legitimate fit here — always-on sensor/voice wake is its actual target market, not a stretch |